DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents

1.1. DisplayPort Terms and Acronyms

The tables list the commonly used DisplayPort terms and acronyms.
Table 1.  DisplayPort Acronyms
Acronym Description
API Application Programming Interface
AUX Auxiliary
bpc Bits per Component
bpp Bits per Pixel
BE Blanking End
BS Blanking Start
DP DisplayPort
DP1.4 DisplayPort version 1.4 in 8B/10B encoding scheme that supports up to HBR3
DP2.0 DisplayPort version 2.0 in 128B/132B encoding scheme that supports up to UHBR20
DPCD DisplayPort Configuration Data
eDP Embedded DisplayPort
EDID Enhanced Display Identification Data
GPU Graphics Processor Unit
HBR High Bit Rate (2.7 Gbps per lane)
HBR2 High Bit Rate 2 (5.4 Gbps per lane)
HBR3 High Bit Rate 3 (8.1 Gbps per lane)
UHBR10 Ultra High Bit Rate 10 (10.0 Gbps per lane)
UHBR13.5 Ultra High Bit Rate 13.5 (13.5 Gbps per lane)
UHBR20 Ultra High Bit Rate 20.0 (20.0 Gbps per lane)
HPD Hot Plug Detect
MST Multi-Stream Transport
Maud M value for audio in DP1.4
Mvid M value for video in DP1.4
Naud N value for audio in DP1.4
Nvid N value for video in DP1.4
VFreq Video frequency in DP2.0
AFreq Audio frequency in DP2.0
RBR Reduced Bit Rate (1.62 Gbps per lane)
RGB Red Green Blue
RX Receiver
SDP Secondary-Data Packet
SR Scrambler Reset
SS SDP Start
SST Single-Stream Transport
TX Transmitter
Table 2.  DisplayPort Terms
Term Definition
Link Symbol Clock (LSym_Clk) Link Symbol clock frequency (f_LSym_Clk) across link rate: -
  • UHBR20 (20.0 Gbps) = 625 MHz
  • UHBR10 (10.0 Gbps) = 312.5 MHz
  • HBR3 (8.1 Gbps) = 810 MHz
  • HBR2 (5.4 Gbps) = 540 MHz
  • HBR (2.7 Gbps) = 270 MHz
  • RBR (1.62 Gbps) = 162 MHz
Note: LSym_Clk is equivalent to LS_Clk in VESA DisplayPort Standard version 2.0.
Link Speed Clock (ls_clk)

Transceiver recovered clock out.

Link Speed clock frequency equals:


Stream Clock or Pixel Clock (Strm_Clk)

Used for transferring stream data into a DisplayPort transmitter within a DisplayPort Source device or from a DisplayPort receiver within a DP Sink device. Video and audio (optional) are likely to have separate stream clocks.

Stream clock frequency (f_Strm_Clk) represent the pixel rate. For example, f_Strm_Clk for 1080p60 (CEA-861-F VIC16) is 148.5 MHz.

Video Clock (vid_clk)

Video clock frequency equals:


8B/10B Channel Coding Channel Coding specification as specified in ANSI INCITS 230. Used at DP1.4 link rates.
128B/132B Channel Coding New channel coding added in DP v2.0 for improving the channel-coding efficiency from 80% of 8B/10B channel coding to 97%.