DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents

5.4. Sideband Channel

The DisplayPort Intel® FPGA IP uses the sideband communication over sideband channel (AUX channel and HPD) to manage topology and virtual channel connection/main link, and performs main link symbol mapping.

The AUX controller interface works with a simple serial-port-type peripheral that operates in a polled mode. It captures all bytes sent from and received by the AUX channel, which is useful for debugging. The IP clocks the AUX controller using a 16 MHz clock input (aux_clk).