DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents

5.2.1. Video Packetizer Path

The video packetizer path provides video data resampling and packetization.

The video packetizer path consists of the following steps:

  1. The mixed-width DCFIFO crosses the video data from the video clock domain (txN_vid_clk) into the main link clock domain (tx_ss_clk) generated by the transceiver. This main clock can be 312.5, 270, 202.5, 135, 81, 67.5, or 40.5 MHz, depending on the actual main link rate requested and the symbols per clock.
  2. The pixel steer block aligns the video data so that the first active pixel of each video line occupies the least significant position.
  3. The pixel packer block decimates the video data to the requested lane count (1, 2, or 4).
  4. The pixel gearbox block resamples the video data according to the specified color depth. You can optimize the gearbox by implementing fewer color depths. For example, you can reduce the resources required to implement the system by supporting only the maximum color depths you need instead of the complete set of color depths specified in the VESA DisplayPort Standard.
  5. The DisplayPort Intel® FPGA IP packetizes the resampled data. The VESA DisplayPort Standard requires data to be sent in a transfer unit (TU), which can be 32 to 64 link symbols long. To reduce complexity, the DisplayPort source uses a fixed 64-symbol TU. The specification also requires that the video data be evenly distributed within the TUs composing a full active video line. A throttle function distributes the data and regulates it to ensure that the TUs leaving the IP are evenly packed. The pixel packetizer punctuates the outgoing video stream with the correct packet comma codes, such as blank end (BE), fill start (FS), and fill end (FE). Internally, the pixel packetizer uses a symbol and a TU counter to ensure that it respects the TU boundaries.
  6. The blank start generator determines when to send the blank start (BS) comma codes with their corresponding video data packets. This block operates in enhanced or standard framing mode.
Note: A minimal DisplayPort system should support both 6 and 8 bpc. The VESA DisplayPort Standard requires support for a mandatory VGA fail-safe mode (640 x 480 at 6 bpc).