DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents Clock Recovery Core Parameters

You can use these parameters to configure the clock recovery core.
Table 12.  Clock Recovery Core Parameters
Parameter Default Value Description
SYMBOLS_PER_CLOCK 4 Specifies the configuration of the DisplayPort RX transceiver used.

Set to 2 for 20-bit mode (Dual symbol) or to 4 for 40-bit mode (Quad symbol).

CLK_PERIOD_NS 10 Specifies the period (in nanoseconds) of the control clock input signal connected to the port.
Note: The recommended control clock frequency is 60 MHz. Set this parameter to 17.
DEVICE_FAMILY Arria V Identifies the device used. The values are Arria V, Cyclone V, and Stratix V.
FIXED_NVID 0 Specifies the configuration of the DisplayPort RX received video clocking used.

Set to 1 for asynchronous clocking, where the Nvid value is fixed to 32’h8000.

Set to 0 if the value of Nvid is a variable of 32'h8000 or any other value.

Note: Most DisplayPort source devices transmit video using asynchronous clocking. For optimized resource usage, Intel recommends you to set the FIXED_NVID parameter to 1.
PIXELS_PER_CLOCK 4 Specifies how many pixels in parallel (for each clock cycle) are gathered from the DisplayPort RX.

Set to 1 for single pixel, 2 for dual, or 4 for quad pixels per clock cycle.

BPP 48 Specifies the width (in bits) of a single pixel.

Set to 18 for 6-bit color, 24 for 8-bit color, and so on up to 48 for 16-bit color.