DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents

10.2.6. DPTX0_MSA_HSW

Address: 0x0025

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 70.  DPTX0_MSA_HSW Bits
Bit Bit Name Function
31:15 Unused
14:0 HSW Main stream attribute horizontal sync width