DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents

10.2.14. DPTX0_MSA_MISC1

Address: 0x002d

Direction: RO

Reset: 0x00000000

Note: For DisplayPort 1.4, bits[2:1] are writeable and control the "3D Stereo Format" as defined in the VESA standard.
Table 78.  DPTX0_MSA_MISC1 Bits
Bit Bit Name Function
31:8 Unused
7:0 MISC1 Main stream attribute MISC1