External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 4/03/2023
Public

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6.4.3.4. Specific Pin Connection Requirements

PLL

You must constrain the PLL reference clock to the address and command sub-bank only.

  • You must constrain the single-ended reference clock to pin index 0 in lane 2.
  • When pin index 0 in lane 2 is used for a single-ended reference clock, you cannot use pin index 1 in lane 2 as a general purpose I/O pin.
  • You must constrain differential reference clocks to pin indices 0 and 1 in lane 2.
  • The sharing of PLL reference clocks across multiple external memory interfaces is permitted; however, pin indices 0 and 1 of Lane 2 of the address and command sub-bank for all slave EMIF interfaces can be used only for supplying reference clocks. Intel recommends that you consider connecting these clocks input pins to a reference clock source to facilitate greater system implementation flexibility.

OCT

You must constrain the RZQ pin to pin index 2 in lane 2 of the address and command sub-bank only.
  • Every EMIF instance requires its own dedicated RZQ pin.
  • The sharing of RZQ pins is not permitted.

Address and Command

For DDR4, you must constrain the ALERT_N pin to the address and command lane only.

  • In three-lane address and command schemes, you can place the ALERT_N pin at pin index 8 in lane 2 only.
  • In four-lane address and command schemes, you can place the ALERT_N pin at pin index 8 in lane 2 or at pin index 8 in lane 3. When you generate the IP, the resulting RTL specifies which connection to use.

DQS/DQ/DBI#

For DDR4 x8 DQS grouping, the following rules apply:

  • You may use pin indices 0, 1, 2, 3, 8, 9, 10, and 11 within a lane for DQ mode pins only.
  • You must use pin index 4 for the DQS_p pin only.
  • You must use pin index 5 for the DQS_n pin only.
  • You must ensure that pin index 7 remains unused. Pin index 7 is not available for use as a general purpose I/O.
  • You must use pin index 6 for the DM/DBI_N pin only.

For DDR4 x4 DQS grouping, the following rules apply:

  • You may use pin indices 0, 1, 2, and 3 within a lane for DQ mode pins for the lower nibble only. Pin rotation within this group is permitted.
  • You must use pin index 4 for the DQS_p pin only of the lower nibble.
  • You must use pin index 5 for the DQS_n pin only of the lower nibble.
  • You may use pin indices 8, 9, 10, and 11 within a lane for the DQ mode pins only for the upper nibble. Pin rotation within this group is permitted.
  • You must use pin index 6 for the DQS_p pin only of the upper nibble.
  • You must use pin index 7 for the DQS_n pin only of the upper nibble.