3.6. Intel® Agilex™ 7 F-Series and I-Series EMIF for Hard Processor Subsystem
To enable connectivity between the Intel® Agilex™ 7 HPS and the Intel® Agilex™ 7 EMIF IP, you must create and configure an instance of the Intel® Agilex™ 7 External Memory Interface for HPS IP core, and use Platform Designer to connect it to the Intel® Agilex™ 7 Hard Processor Subsystem instance in your system.
The Intel® Agilex™ 7 Hard Processor Subsystem is compatible with the following external memory configurations:
|Maximum memory clock frequency||1600MHz|
|Configuration||Hard PHY with hard memory controller|
|Clock rate of PHY and hard memory controller||Half-rate, Quarter-rate|
|Data width (without ECC)||16-bit, 32-bit, 64-bit|
|Data width (with ECC)||24-bit, 40-bit, 72-bit|
|DQ width per group||x8|
|Memory format|| Supports up to 32GB of memory.
* Only one differential memory clock output is provided; therefore, you must do one of the following:
- Use single-rank discrete components, UDIMMs, or SODIMMs.
- Use dual-rank components that require only one clock input (for example, dual-die packages).
- Use RDIMMs that rely only on one clock input.
- Use the single clock output to drive both clock inputs and confirm through simulation that the memory interface margins are not adversely affected by the double loading of the clock output.
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