External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.3. Data Transfer

The following methods of data transfer reduce the efficiency of your controller:
  • Performing individual read or write accesses is less efficient.
  • Switching between read and write operation reduces the efficiency of the controller.
  • Performing read or write operations from different rows within a bank or in a different bank—if the bank and a row you are accessing is not already open—also affects the efficiency of your controller.