External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Specific Pin Connection Requirements


You must constrain the PLL reference clock to the address and command sub-bank only.

  • You must constrain the single-ended reference clock to pin index 0 in lane 2.
  • When pin index 0 in lane 2 is used for a single-ended reference clock, you cannot use pin index 1 in lane 2 as a general purpose I/O pin.
  • You must constrain differential reference clocks to pin indices 0 and 1 in lane 2.
  • The sharing of PLL reference clocks across multiple external memory interfaces is permitted; however, pin indices 0 and 1 of Lane 2 of the address and command sub-bank for all slave EMIF interfaces can be used only for supplying reference clocks. Intel recommends that you consider connecting these clocks input pins to a reference clock source to facilitate greater system implementation flexibility.


You must constrain the RZQ pin to pin index 2 in lane 2 of the address and command sub-bank only.
  • Every EMIF instance requires its own dedicated RZQ pin.
  • The sharing of RZQ pins is not permitted.

Did you find the information on this page useful?

Characters remaining:

Feedback Message