External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 4/03/2023

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4.1.2. Intel® Agilex™ 7 EMIF IP Interfaces for QDR-IV

The interfaces in the Intel® Agilex™ 7 External Memory Interface IP each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types for QDR-IV.
Table 39.  Interfaces for QDR-IV
Interface Name Interface Type Description
local_reset_req Conduit Local reset request. Output signal from local_reset_combiner
local_reset_status Conduit Local reset status. Input signal to the local_reset_combiner
pll_ref_clk Clock Input PLL reference clock input
pll_locked Conduit PLL locked signal
oct Conduit On-Chip Termination (OCT) interface
mem Conduit Interface between FPGA and external memory
status Conduit PHY calibration status interface
afi_reset_n Reset Output AFI reset interface
afi_clk Clock Output AFI clock interface
afi_half_clk Clock Output AFI half-rate clock interface
afi Conduit Altera PHY Interface (AFI)
emif_usr_reset_n Reset Output User clock domain reset interface
emif_usr_clk Clock Output User clock interface
ctrl_amm Avalon Memory-Mapped Slave Controller Avalon Memory-Mapped interface
emif_calbus Conduit EMIF calibration component interface
emif_calbus_clk Clock Output EMIF calibration component clock input interface