Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 10/04/2021
Public

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1.3.2.1. Using Simulation Signal Activity Data in Power Analysis

You can specify a Verilog Value Change Dump File (.vcd) generated by simulating a placed and routed gate-level netlist in a supported1 simulator as the source of signal activity data for power analysis.

Third-party simulators can output a .vcd that contains signal activity and static probability information that inform the power analysis. The generated .vcd includes all of the routing resources and the exact logic array resource usage.

Figure 6. Using Simulation Signal Activity Data in Power Analysis

To improve accuracy of power analysis, you can generate a Standard Delay Output (.sdo) file that includes back-annotated delay estimates of the instances of core atoms for ModelSim* simulation. ModelSim* simulation can then output a more accurate .vcd for use as power analysis input. You must run the Fitter (Finalize) command before generating the .sdo. Note: To improve accuracy of power analysis, the Intel® Quartus® Prime EDA Netlist writer can generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for a design's netlist for use during simulation in ModelSim* . Although the .sdo only contains delay estimates and imprecise timing information, including the .sdo in simulation results in a more accurate output .vcd for power analysis.

Note: The EDA Netlist Writer currently supports .sdo file generation only for Verilog .vo simulation in the ModelSim* simulator (not ModelSim* - Intel® FPGA Edition) for Intel® Stratix® 10 designs. The EDA Netlist Writer does not currently support .sdo file generation for any other simulator or device family.
1 ModelSim* , ModelSim* - Intel® FPGA Edition, QuestaSim, Active-HDL, NCSim, VCS* , VCS* MX, Riviera-PRO*

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