2.3.1. Power-Driven Synthesis
The Power Optimization During Synthesis logic option determines how aggressively Analysis & Synthesis optimizes the design for power. To access this option at a project level, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).
|Settings||Description||Optimization Techniques Included|
|Off||The Compiler does not perform netlist, placement, or routing optimizations to minimize power.||-|
|Normal compilation (Default)||The Compiler applies low compute effort algorithms to minimize power through netlist optimizations that do not reduce design performance.||
|Extra effort||Besides the techniques in the Normal compilation setting, the Compiler applies high-compute-effort algorithms to minimize power through netlist optimizations. Selecting this option might impact performance.||
You can also control memory optimization options from the Intel® Quartus® Prime Settings dialog box. The Default Parameters page allows you to edit the Low_Power_Mode parameter. The settings for this parameter are equivalent to the values of the Power Optimization During Synthesis logic options. The Low_Power_Mode parameter always takes precedence over the Optimize Power for Synthesis option for power optimization on memory.
|Parameter Value||Equivalent Setting in Power Optimization During Synthesis Logic Option|
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