220.127.116.11. Using Simulation Signal Activity Data in Power Analysis 18.104.22.168. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 22.214.171.124. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 126.96.36.199. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation Power Analysis Flow 1.5.2. Modular Design Simulation Power Analysis Flow 1.5.3. Multiple Simulation Power Analysis Flow 1.5.4. Overlapping Simulation Power Analysis Flow 1.5.5. Partial Design Simulation Power Analysis Flow 1.5.6. Vectorless Estimation Power Analysis Flow
2.4.1. Clock Power Management 2.4.2. Pipelining and Retiming 2.4.3. Architectural Optimization 2.4.4. I/O Power Guidelines 2.4.5. Dynamically Controlled On-Chip Terminations (OCT) 2.4.6. Memory Optimization (M20K/MLAB) 2.4.7. DDR Memory Controller Settings 2.4.8. DSP Implementation 2.4.9. Reducing High-Speed Tile (HST) Usage 2.4.10. Unused Transceiver Channels 2.4.11. Periphery Power reduction XCVR Settings
2.4.6. Memory Optimization (M20K/MLAB)
M20K memory blocks represent a big part of the power consumption in a design. The Fitter RAM Summary Report displays the utilization of the memory blocks in different parts of the design.
Figure 33. Fitter RAM Summary Report
Some guidelines to optimize the use of memories are:
- Port shallow memories from M20K to MLAB.
For example, implement in HDL with ramstyle attribute:
(* ramstyle = "MLAB" *) reg [0:7] my_ram[0:63];
- Avoid read-during-write behavior and set to Don’t care (at the HDL level) wherever possible.
Read-during-write behavior impact the power of single-port and bidirectional dual-port RAMs. Don’t care allows an optimization that sets the read-enable signal to the inversion of the existing write-enable signal (if one exists). This allows the core of the RAM to shut down, which prevents switching, saving a significant amount of power.
- Pack input/output registers in M20K.
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