22.214.171.124.1. RTL Simulation Limitation
RTL simulation may not provide signal activities for all registers in the post-fitting netlist because synthesis loses some register names. For example, synthesis might automatically transform state machines and counters, thus changing the names of registers in those structures. As a result, a large number of nodes in the .vcd file may not match the nodes in your design netlist, which can result in the power analysis results being less accurate or of lower confidence.
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