Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 10/04/2021
Public

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Document Table of Contents

2.6. Power Optimization Revision History

The following revision history applies to this chapter:

Table 13.  Document Revision History
Document Version Intel® Quartus® Prime Version Changes
2021.10.04 21.3.0 Modified the Compiler Settings topic.
2020.12.07 18.1.0 Added note to the Toggle Rate topic.
2019.08.02 18.1.0
  • Corrected typo in "Viewing Clock Details in the Chip Planner" topic.
  • Corrected typo in "Pipelining and Retiming" topic.
  • Corrected typo in "Implementation" topic.
  • Updated "DDR Memory Controller Settings" topic for latest IP name and to correct typos.
  • Corrected typo in "Pipeline Logic to Reduce Glitching" topic.
2018.09.24 18.1.0
  • Added topic: Factors Affecting Power Consumption, moved from chapter: Power Analysis
  • Extended content about Power Optimization Advisor with a description of recommendations.
  • Added design guidelines: Memories (M20K/MLAB), DDR Memory Controller Settings, DSP Implementation, Reducing High-Speed Tile (HST) Usage, Unused Transceiver Channels, Periphery Power reduction XCVR Settings
  • Removed content referring to device families not supported in Intel Quartus Prime Pro Edition.
2018.06.11 18.0.0
  • Moved general information about the Design Space Explorer (DSE II) to the Design Optimization User Guide, left a section about using DSE II for Power-Driven Optimization.
2018.05.07 18.0.0
  • Moved general information about the Design Space Explorer (DSE II) to the Design Optimization User Guide, left a section about using DSE II for Power-Driven Optimization.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Removed statement of support for gate-level timing simulation.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
  • Updated screenshot for DSE II GUI.
  • Added information about remote hosts for DSE II.
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Updated DSE II GUI and optimization settings.
2014.06.30 14.0.0 Updated the format.
May 2013 13.0.0 Added a note to “Memory Power Reduction Example” on Qsys and SOPC Builder power savings limitation for on-chip memory block.
June 2012 12.0.0 Removed survey link.
November 2011 10.0.2 Template update.
December 2010 10.0.1 Template update.
July 2010 10.0.0
  • Was chapter 11 in the 9.1.0 release
  • Updated Figures 14-2, 14-3, 14-6, 14-18, 14-19, and 14-20
  • Updated device support
  • Minor editorial updates
November 2009 9.1.0
  • Updated Figure 11-1 and associated references
  • Updated device support
  • Minor editorial update
March 2009 9.0.0
  • Was chapter 9 in the 8.1.0 release
  • Updated for the Quartus II software release
  • Added benchmark results
  • Removed several sections
  • Updated Figure 13–1, Figure 13–17, and Figure 13–18
November 2008 8.1.0
  • Changed to 8½” × 11” page size
  • Changed references to altsyncram to RAM
  • Minor editorial updates
May 2008 8.0.0
  • Added support for Stratix IV devices
  • Updated Table 9–1 and 9–9
  • Updated “Architectural Optimization” on page 9–22
  • Added “Dynamically-Controlled On-Chip Terminations” on page 9–26
  • Updated “Referenced Documents” on page 9–29
  • Updated references

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