2.3.2. Power-Driven Fitter
|Off||The Fitter does not perform optimizations to minimize power.|
|Normal compilation (Default)||
The Fitter applies low compute effort algorithms to minimize power through placement and routing optimizations. These techniques do not reduce design performance.
Includes DSP optimizations that create power-efficient DSP block configurations for DSP functions.
|Extra effort||Besides the optimization techniques of the Normal Compilation option, the Fitter applies high compute effort algorithms to minimize power through placement and routing optimizations. These techniques might impact performance.
The Extra effort setting for the Fitter requires extensive effort to optimize the design for power and can increase compilation time.
The Extra effort setting the Fitter works to minimize power even after the design meets timing requirements by moving the logic closer during placement to localize high-toggling nets and choosing routes with low capacitance.
The Extra effort setting uses a Value Change Dump (.vcd) file that guides the Fitter to fully optimize the design for power, based on the signal activity of the design. The best power optimization during fitting results from using the most accurate signal activity information. If there is no .vcd file, the Intel® Quartus® Prime software estimates the signal activities from the settings in the Power Analyzer Settings page in the Settings dialog box, such as assignments, clock assignments, and vectorless estimation values.
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