Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 10/04/2021
Public

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1.3.2.1.1. Generating Signal Activity Data for Power Analysis

Follow these steps to generate and use simulation signal activity data for power analysis:

  1. To run full compilation on your design, click Processing > Start Compilation.
  2. To specify settings for output of simulation files, click Assignments > Settings > EDA Tool Settings > Simulation. Select your simulator in Tool name and the Format for output netlist and Output directory.
  3. Turn on Map illegal HDL characters. This setting directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL, and results in more accurate data for power analysis.
    Figure 7. EDA Tool Settings for Simulation
  4. For Intel® Stratix® 10 designs, to generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for power analysis, refer to Generating Standard Delay Output for Power Analysis.
  5. In the Intel® Quartus® Prime software, click Assignments > Settings > Power Analyzer Settings.
  6. Under Input file, turn on Use input files to initialize toggle rates and static probabilities during power analysis.
    Figure 8. Specifying Power Analysis Input Files
  7. To specify a .vcd for power analysis, click Add and specify the File name, Entity, and Simulation period for the .vcd, and click OK.
  8. To enable glitch filtering during power analysis with the .vcd you generate, turn on Perform glitch filtering on VCD files.
  9. To run the power analysis, click Start on the Power Analysis step in the Compilation Dashboard. View the toggle rates in the power analysis results.

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