Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 10/04/2021
Public

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2.3.6. Assignment Editor Options

The Assignment Editor allows you to select Optimization Technique & Synthesis Power Optimization for individual modules. With this feature, you can focus on the parts of the design that require more work.

The Optimization Technique logic option specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or minimize logic usage.

Figure 20. Optimization Technique Options

The Power Optimization During Synthesis logic option determines how aggressively Analysis & Synthesis optimizes the design for power.

Figure 21. Power Optimization During Synthesis Options
Table 11.  Power Optimization During Synthesis Options
Settings Description Optimization Techniques Included
Off The Compiler does not perform netlist, placement, or routing optimizations to minimize power. -
Normal compilation (Default) The Compiler applies low compute effort algorithms to minimize power through netlist optimizations that do not reduce design performance.
  • Memory block optimization
  • Power-aware logic mapping
Extra effort Besides the techniques in the Normal compilation setting, the Compiler applies high-compute-effort algorithms to minimize power through netlist optimizations. Selecting this option might impact performance.
  • Memory block optimization
  • Power-aware logic mapping
  • Power-aware memory balance

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