2.3.6. Assignment Editor Options
The Optimization Technique logic option specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or minimize logic usage.
The Power Optimization During Synthesis logic option determines how aggressively Analysis & Synthesis optimizes the design for power.
|Settings||Description||Optimization Techniques Included|
|Off||The Compiler does not perform netlist, placement, or routing optimizations to minimize power.||-|
|Normal compilation (Default)||The Compiler applies low compute effort algorithms to minimize power through netlist optimizations that do not reduce design performance.||
|Extra effort||Besides the techniques in the Normal compilation setting, the Compiler applies high-compute-effort algorithms to minimize power through netlist optimizations. Selecting this option might impact performance.||
Did you find the information on this page useful?