HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

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1.2. Simulating the Design

The HDMI testbench simulates a serial loopback design from a TX instance to an RX instance. Internal video pattern generator, audio sample generator, sideband data generator, and auxiliary data generator modules drive the HDMI TX instance and the serial output from the TX instance connects to the RX instance in the testbench.
Figure 3. Design Simulation Flow
  1. Go to the desired simulation folder.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    Table 1.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Riviera-PRO* /simulation/aldec
    In the command line, type
    vsim -c -do aldec.do
    ModelSim* /simulation/mentor
    In the command line, type
    vsim -c -do mentor.do
    VCS* /simulation/synopsys/vcs
    In the command line, type
    source vcs_sim.sh
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type
    source vcsmx_sim.sh
    Xcelium* Parallel /simulation/xcelium In the command line, type
    source xcelium_sim.sh
    A successful simulation ends with the following message:
    # SYMBOLS_PER_CLOCK 	= 2
    # VIC               	= 4
    # FRL_RATE          	= 0
    # BPP               	= 0
    # AUDIO_FREQUENCY (kHz)  = 48
    # AUDIO_CHANNEL     	= 8
    # Simulation pass

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