HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

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4.3.5.1. Push Buttons and LED Functions

Use the push buttons and LED functions on the board to control your demonstration.
Table 55.  Push Button and LED Indicators (SUPPORT FRL = 0)
Push Button/LED Functions
cpu_resetn Press once to perform system reset.
user_pb[0] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[1]
  • Press and hold to instruct the TX core to send the DVI encoded signal.
  • Release to send the HDMI encoded signal.
  • Make sure the incoming video is in 8 bpc RGB color space.
user_pb[2]
  • Press and hold to instruct the TX core to stop sending the InfoFrames from the sideband signals.
  • Release to resume sending the InfoFrames from the sideband signals.

user_led[0]

RX HDMI PLL lock status.
  • 0: Unlocked
  • 1: Locked

user_led[1]

RX HDMI core lock status
  • 0: At least 1 channel unlocked
  • 1: All 3 channels locked

user_led[2]

RX HDCP1x IP decryption status.
  • 0: Inactive
  • 1: Active

user_led[3]

RX HDCP2x IP decryption status.
  • 0: Inactive
  • 1: Active

user_led[4]

TX HDMI PLL lock status.
  • 0: Unlocked
  • 1: Locked

user_led[5]

TX transceiver PLL lock status.
  • 0: Unlocked
  • 1: Locked

user_led[6]

TX HDCP1x IP encryption status.
  • 0: Inactive
  • 1: Active

user_led[7]

TX HDCP2x IP encryption status.
  • 0: Inactive
  • 1: Active
Table 56.  Push Button and LED Indicators (SUPPORT FRL = 1)
Push Button/LED Functions
cpu_resetn Press once to perform system reset.
user_dipsw

User-defined DIP switch to toggle the passthrough mode.

  • OFF (default position) = Passthrough

    HDMI RX on the FPGA gets the EDID from external sink and presents it to the external source it is connected to.

  • ON = You may control the RX maximum FRL rate from the Nios® II terminal. The command modifies the RX EDID by manipulating the maximum FRL rate value.

Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates.

user_pb[0] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[1] Reserved.
user_pb[2] Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
user_led_g[0] RX FRL clock PLL lock status.
  • 0: Unlocked
  • 1: Locked
user_led_g[1] RX HDMI video lock status.
  • 0: Unlocked
  • 1: Locked
user_led_g[2] RX HDCP1x IP decryption status.
  • 0: Inactive
  • 1: Active
user_led_g[3] RX HDCP2x IP decryption status.
  • 0: Inactive
  • 1: Active
user_led_g[4] TX FRL clock PLL lock status.
  • 0: Unlocked
  • 1: Locked
user_led_g[5] TX HDMI video lock status.
  • 0 = Unlocked
  • 1 = Locked
user_led_g[6] TX HDCP1x IP encryption status.
  • 0: Inactive
  • 1: Active
user_led_g[7]
TX HDCP2x IP encryption status.
  • 0: Inactive
  • 1: Active

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