HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

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2.15.3. Clock Frequency Measurement

Use this feature to check the frequency for the different clocks.
  1. In the hdmi_rx_top and hdmi_tx_top files, uncomment “//`define DEBUG_EN 1”.
  2. Add the refclock_measure signal from each mr_rate_detect instance to the Signal Tap Logic Analyzer to get the clock frequency of each clock (in 10 ms duration).
  3. Compile the design with Signal Tap Logic Analyzer.
  4. Program the SOF file and run the Signal Tap Logic Analyzer.
Table 26.  Clocks
Module mr_rate_detect Instance Clock to be Measured
hdmi_rx_top rx_pll_tmds RX CDR reference clock 0
rx_clk0_freq RX transceiver clock out from channel 0
rx_vid_clk_freq RX video clock
rx_frl_clk_freq RX FRL clock
rx_hsync_freq Hsync frequency of the received video frame
hdmi_tx_top tx_clk0_freq TX transceiver clock out from channel 0
vid_clk_freq TX video clock
frl_clk_freq TX FRL clock
tx_hsync_freq Hsync frequency of the video frame to be transmitted

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