HDMI Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683156
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

2.5.1. HDMI TX Components

The HDMI TX top components include the TX core top-level components, and the IOPLL, transceiver PHY reset controller, transceiver native PHY, TX PLL, TX reconfiguration management, and the output buffer blocks.
Figure 7. HDMI TX Top Components
Table 8.  HDMI TX Top Components
Module Description
HDMI TX Core

The IP receives video data from the top level and performs auxiliary data encoding, audio data encoding, video data encoding, scrambling, TMDS encoding or packetization.

IOPLL The IOPLL (iopll_frl) generates the FRL clock for the TX core. This reference clock receives the TX FPLL output clock.

FRL clock frequency = Data rate per lanes x 4 / (FRL characters per clock x 18)

Transceiver PHY Reset Controller

The Transceiver PHY reset controller ensures a reliable initialization of the TX transceivers. The reset input of this controller is triggered from the top level, and it generates the corresponding analog and digital reset signal to the Transceiver Native PHY block according to the reset sequencing inside the block.

The tx_ready output signal from this block also functions as a reset signal to the HDMI Intel® FPGA IP to indicate the transceiver is up and running, and ready to receive data from the core.

Transceiver Native PHY

Hard transceiver block that receives the parallel data from the HDMI TX core and serializes the data from transmitting it.

Note: To meet the HDMI TX inter-channel skew requirement, set the TX channel bonding mode option in the Intel® Arria® 10 Transceiver Native PHY parameter editor to PMA and PCS bonding. You also need to add the maximum skew (set_max_skew) constraint requirement to the digital reset signal from the transceiver reset controller (tx_digitalreset) as recommended in the Intel® Arria® 10 Transceiver PHY User Guide.
TX PLL

The transmitter PLL block provides the serial fast clock to the Transceiver Native PHY block. For this HDMI Intel® FPGA IP design example, fPLL is used as TX PLL.

TX PLL has two reference clocks.

  • Reference clock 0 is connected to the programmable oscillator (with TMDS clock frequency) for TMDS mode. In this design example, RX TMDS clock is used to connect to reference clock 0 for TMDS mode. Intel recommends you to use programmable oscillator with TMDS clock frequency for reference clock 0.
  • Reference clock 1 is connected to a fixed 100 MHz clock for FRL mode.
TX Reconfiguration Management
  • In TMDS mode, the TX reconfiguration management block reconfigures the TX PLL for different output clock frequency according to the TMDS clock frequency of the specific video.
  • In FRL mode, the TX reconfiguration management block reconfigures the TX PLL to supply the serial fast clock for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps and 12 Gbps according to FRL_Rate field in the 0x31 SCDC register.
  • The TX reconfiguration management block switches the TX PLL reference clock between reference clock 0 for TMDS mode and reference clock 1 for FRL mode.
Output buffer This buffer acts as an interface to interact the I2C interface of the HDMI DDC and redriver components.
Table 9.  Transceiver Data Rate and Oversampling Factor Each Clock Frequency Range
Mode Data Rate Oversampler 1 (2x oversample) Oversampler 2 (4x oversample) Oversample Factor Oversampled Data Rate (Mbps)
TMDS 250–1000 On On 8 2000–8000
TMDS 1000–6000 On Off 2 2000–12000
FRL 3000 Off Off 1 3000
FRL 6000 Off Off 1 6000
FRL 8000 Off Off 1 8000
FRL 10000 Off Off 1 10000
FRL 12000 Off Off 1 12000
Figure 8. TX Reconfiguration Sequence Flow
Level Two Title