HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

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3.8. Design RTL Parameters

Use the HDMI TX and RX Top RTL parameters to customize the design example.

Most of the design parameters are available in the Design Example tab of the HDMI Intel® FPGA IP parameter editor. You can still change the design example settings you made in the parameter editor through the RTL parameters.

Table 46.  HDMI RX Top Parameters
Parameter Value Description
SUPPORT_DEEP_COLOR
  • 0: No deep color
  • 1: Deep color
Determines if the core can encode deep color formats.
SUPPORT_AUXILIARY
  • 0: No AUX
  • 1: AUX
Determines if the auxiliary channel encoding is included.
SYMBOLS_PER_CLOCK 8 Supports 8 symbols per clock for Intel® Arria® 10 devices.
SUPPORT_AUDIO
  • 0: No audio
  • 1: Audio
Determines if the core can encode audio.
EDID_RAM_ADDR_WIDTH ( Intel® Quartus® Prime Standard Edition) 8 (Default value) Log base 2 of the EDID RAM size.
BITEC_DAUGHTER_CARD_REV
  • 0: Not targeting any Bitec HDMI daughter card
  • 4: Supports Bitec HDMI daughter card revision 4
  • 6: Targeting Bitec HDMI daughter card revision 6
  • 11: Targeting Bitec HDMI daughter card revision 11 (default)
Specifies the revision of the Bitec HDMI daughter card used. When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity.
POLARITY_INVERSION
  • 0: Invert polarity
  • 1: Do not invert polarity
Set this parameter to 1 to invert the value of each bit of the input data. Setting this parameter to 1 assigns 4'b1111 to the rx_polinv port of the RX transceiver.
Table 47.  HDMI TX Top Parameters
Parameter Value Description
USE_FPLL 1 Supports fPLL as TX PLL only for Intel® Cyclone® 10 GX devices. Always set this parameter to 1.
SUPPORT_DEEP_COLOR
  • 0: No deep color
  • 1: Deep color
Determines if the core can encode deep color formats.
SUPPORT_AUXILIARY
  • 0: No AUX
  • 1: AUX
Determines if the auxiliary channel encoding is included.
SYMBOLS_PER_CLOCK 8 Supports 8 symbols per clock for Intel® Arria® 10 devices.
SUPPORT_AUDIO
  • 0: No audio
  • 1: Audio
Determines if the core can encode audio.
BITEC_DAUGHTER_CARD_REV
  • 0: Not targeting any Bitec HDMI daughter card
  • 4: Supports Bitec HDMI daughter card revision 4
  • 6: Targeting Bitec HDMI daughter card revision 6
  • 11: Targeting Bitec HDMI daughter card revision 11 (default)
Specifies the revision of the Bitec HDMI daughter card used. When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity.
POLARITY_INVERSION
  • 0: Invert polarity
  • 1: Do not invert polarity
Set this parameter to 1 to invert the value of each bit of the input data. Setting this parameter to 1 assigns 4'b1111 to the tx_polinv port of the TX transceiver.