HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

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2.12. Hardware Setup

The HDMI FRL-enabled design example is HDMI 2.1 capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the HDMI sink input. The design supports both HDMI 2.1 or HDMI 2.0/1.4b source and sink.
  1. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  2. The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
  3. The HDMI source port of the FMC daughter card transmits the image to a monitor.
Note: If you want to use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Intel® Arria® 10 FPGA development kit and Bitec HDMI 2.1 daughter card. You may modify the settings for your own board.
On-board Push Button and User LED Functions
Push Button/LED Function
cpu_resetn

Press once to perform system reset.

user_dipsw

User-defined DIP switch to toggle the passthrough mode.

  • OFF (default position) = Passthrough

    HDMI RX on the FPGA gets the EDID from external sink and presents it to the external source it is connected to.

  • ON = You may control the RX maximum FRL rate from the Nios® II terminal. The command modifies the RX EDID by manipulating the maximum FRL rate value.

Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates.

user_pb[0]

Press once to toggle the HPD signal to the standard HDMI source.

user_pb[1]

Reserved.

user_pb[2]
Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
USER_LED[0]
RX TMDS clock PLL lock status.
  • 0 = Unlocked
  • 1 = Locked
USER_LED[1]
RX transceiver ready status.
  • 0 = Not ready
  • 1 = Ready
USER_LED[2]
RX link speed clock PLL, and RX video and FRL clock PLL lock status.
  • 0 = Either one of the RX clock PLL is unlocked
  • 1 = Both RX clock PLLs are locked
USER_LED[3]
RX HDMI core alignment and deskew lock status.
  • 0 = At least 1 channel is unlocked
  • 1 = All channels are locked
USER_LED[4]
RX HDMI video lock status.
  • 0 = Unlocked
  • 1 = Locked
USER_LED[5]
TX link speed clock PLL, and TX video and FRL clock PLL lock status.
  • 0 = Either one of the TX clock PLL is unlocked
  • 1 = Both TX clock PLLs are locked
USER_LED[6]
TX transceiver ready status.
  • 0 = Not ready
  • 1 = Ready
USER_LED[7]
TX link training status.
  • 0 = Failed
  • 1 = Passed

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