2.12. Hardware Setup
- The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
- The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
- The HDMI source port of the FMC daughter card transmits the image to a monitor.
Press once to perform system reset.
User-defined DIP switch to toggle the passthrough mode.
Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates.
Press once to toggle the HPD signal to the standard HDMI source.
Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
RX TMDS clock PLL lock status.
RX transceiver ready status.
RX link speed clock PLL, and RX video and FRL clock PLL lock status.
RX HDMI core alignment and deskew lock status.
RX HDMI video lock status.
TX link speed clock PLL, and TX video and FRL clock PLL lock status.
TX transceiver ready status.
TX link training status.
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