2.9. Clocking Scheme
|Clock||Signal Name in Design||Description|
A free running 100 MHz clock for these components:
A 100 MHz clock input that clocks I2C slave, output buffers, SCDC registers, and link training process in the HDMI RX core, and EDID RAM.
|TX PLL Reference Clock 0||tx_tmds_clk||
Reference clock 0 to the TX PLL. The clock frequency is the same as the expected TMDS clock frequency from the HDMI TX TMDS clock channel. This reference clock is used in TMDS mode.
For this HDMI design example, this clock is connected to the RX TMDS clock for demonstration purpose. In your application, you need to supply a dedicated clock with TMDS clock frequency from a programmable oscillator for better jitter performance.
Note: Do not use a transceiver RX pin as a TX PLL reference clock. Your design will fail to fit if you place the HDMI TX refclk on an RX pin.
|TX PLL Reference Clock 1||txfpll_refclk1/rxphy_cdr_refclk1||
Reference clock to the TX PLL and RX CDR, as well as IOPLL for vid_clk. The clock frequency is 100 MHz.
|TX PLL Serial Clock||tx_bonding_clocks||
Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.
|TX Transceiver Clock Out||tx_clk||
Clock out recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.
TX transceiver clock out frequency = Transceiver data rate/Transceiver width
For this HDMI design example, the TX transceiver clock out from channel 0 clocks the TX transceiver core input (tx_coreclkin), link speed IOPLL (pll_hdmi) reference clock, and the video and FRL IOPLL (pll_vid_frl) reference clock.
Video clock to TX and RX core. The clock runs at a fixed frequency of 225 MHz.
|TX/RX FRL Clock||tx_frl_clk/rx_frl_clk||
FRL clock to for TX and RX core.
|RX TMDS Clock||rx_tmds_clk||
TMDS clock channel from the HDMI RX connector and connects to an IOPLL to generate the reference clock for CDR reference clock 0. The core uses this clock when it is in TMDS mode.
|RX CDR Reference Clock 0||rxphy_cdr_refclk0||
Reference clock 0 to RX CDR. This clock is derived from the RX TMDS clock. The RX TMDS clock frequency ranges from 25 MHz to 340 MHz while the RX CDR minimum reference clock frequency is 50 MHz.
An IOPLL is used to generate a 5 clock frequency for the TMDS clock between 25 MHz to 50 MHz and generate the same clock frequency for the TMDS clock between 50 MHz - 340 MHz.
|RX Transceiver Clock Out||rx_clk||
Clock out recovered from the transceiver, and the frequency varies depending on the data rate and transceiver width.
RX transceiver clock out frequency = Transceiver data rate/Transceiver width
For this HDMI design example, the RX transceiver clock out from channel 1 clocks the RX transceiver core input (rx_coreclkin) and FRL IOPLL (pll_frl) reference clock.
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