HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.6. Debug Guidelines

This section describes the useful HDCP status signal and software parameters that can be used for debugging. It also contains frequently asked questions (FAQ) about running the design example.

Did you find the information on this page useful?

Characters remaining:

Feedback Message