F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

4.2. TLP Bypass Mode

The F-Tile Avalon-ST IP for PCIe includes a TLP Bypass mode for both downstream and upstream ports to allow the implementation of advanced features such as:
  • The upstream port or the downstream port of a switch.
  • A custom implementation of a Transaction Layer to meet specific user requirements.
Table 52.  Supported TLP Bypass ConfigurationsUP=Upstream Port ; DN=Downstream Port; EP=Endpoint
IP Mode Port Mode











The F-Tile Avalon-ST IP IP in TLP Bypass mode still includes some of the PCIe configuration space registers related to link operation.

F-Tile Avalon-ST IP interfaces with the application logic via the Avalon-ST interface (for all TLP traffic), the User Avalon-MM interface (via Hard IP Reconfiguration interface, for Lite TL’s configuration registers access) and other miscellaneous signals.

In TLP bypass mode, F-Tile supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code. However, in TLP bypass mode, CvP init and update are not supported.

When the TLP Bypass feature is enabled, the F-Tile Avalon-ST IP does not process received TLPs internally but outputs them to the user application. This allows the application to implement a custom Transaction Layer.

Note: In TLP Bypass mode, the PCIe Hard IP does not generate/check the ECRC and will not remove it if the received TLP has the ECRC.
Figure 52. TLP Bypass Mode