F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

5.18. PTM Interface Signals

Table 80.  PTM Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
ptm_clk_updated_o Output EP coreclkout_hip

An active high pulse indicating that the ptm_local_clock[63:0] contains the new updated PTM time/clock.

This signal can only be asserted when ptm_context_valid = ‘1’.

ptm_local_clock_o[63:0] Output EP coreclkout_hip

Calculated local PTM clock value

ptm_context_valid_o Output EP coreclkout_hip PTM context valid indication.




Indicates that the controller should update the PTM Requester Context and Clock now. This is used when manual PTM context update mode is selected.

This signals remain asserted until new ptm_clk_updated_o is asserted. Between two manual update requests, you are required to ensure this signal is deasserted for at least 32 ns.