F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

A.1. Configuration Space Registers

In addition to accessing the Endpoint's configuration space registers by sending Configuration Read/Write TLPs via the Avalon® -ST interface, the application logic can also gain read access to these registers via the Configuration Output Interface (tl_cfg*). Furthermore, the Hard IP Reconfiguration Interface (a User Avalon® -MM interface) also provides read/write access to these registers.

For signal timings on the User Avalon® -MM interface, refer to the Avalon® Interface Specifications document.

The table PCIe Configuration Space Registers describes the registers for each PF. To calculate the address for a particular register in a particular PF, add the offset for that PF from the table Configuration Space Offsets to the byte address for that register as given in the table PCIe Configuration Space Registers.

Table 125.  Configuration Space Offsets
Registers User Avalon® -MM Offsets
Physical function 0 0x0000
Physical function 1 0x1000
Physical function 2 0x2000
Physical function 3 0x3000
Physical function 4 0x4000
Physical function 5 0x5000
Physical function 6 0x6000
Physical function 7 0x7000
Port Configuration and Status Register 0x14000
Debug (DBI) Register 0x14200
Completion Timeout Register 0x90000
Table 126.  PCIe Configuration Space Registers for x16/x8/x4 Controllers
Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

x16 = 0x000 : 0x03F

x8 = 0x000 : 0x03F

x4) = 0x000 : 0x03F

PCI Header Type 0/1 Configuration Registers Type 0/1 Configuration Space Header

x16 = 0x040 : 0x047

x8 = 0x040 : 0x047

x4 = 0x040 : 0x047

Power Management PCI Power Management Capability Structure

x16 = 0x050 : 0x067

x8 = 0x050 : 0x067

x4 = 0x050 : 0x067

MSI Capability

MSI Capability Structure, see also PCI Local Bus Specification

x16 = 0x070 : 0xAB

x8 = 0x070 : 0xAB

x4 = 0x070 : 0xAB

PCI Express Capability PCI Express Capability Structure

x16 = 0x0B0 : 0xBB

x8 = 0x0B0 : 0xBB

x4 = 0x0B0 : 0xBB

MSI-X Capability MSI-X Capability Structure, see also PCI Local Bus Specification

x16 = 0x0BC : 0x0FC

x8 = 0x0BC : 0x0FC

x4 = 0x0BC : 0x0FC

Reserved N/A

x16 = 0x100 : 0x147

x8 = 0x100 : 0x147

x4 = 0x100 : 0x147

Advanced Error Reporting (AER) Advanced Error Reporting Capability Structure

x16, x8, x4 = 0x148 - 0x163

Virtual Channel Capability Virtual Channel Capability Structure

x16, x8, x4 = 0x164 - 0x173

Device Serial Number Capability

Device Serial Number Capability Structure

x16, x8, x4: 0x174 - 0x17B

Alternative Routing-ID Implementation (ARI) ARI Capability Structure

x16 = 0x184 - 0x1B3

x8 = 0x184 - 0x1A3

x4 = 0x184 - 0x1A3

Secondary PCI Express Extended Capability Header

PCI Express Extended Capability

x16 = 0x1B4 - 0x1E3

x8 = 0x1A4 - 0x1CB

x4 = 0x1A4 - 0x1C7

Physical Layer 16.0 GT/s Extended Capability Physical Layer 16.0 GT/s Extended Capability Structure

x16 = 0x1E4 - 0x22B

x8 = 0x1CC - 0x1F3

x4 = 0x1C8 - 0x1DF

Margining Extended Capability Margining Extended Capability Structure

x16 = 0x22C - 0x26B

x8 = 0x1F4 - 0x233

SR-IOV Capability SR-IOV Capability Structure

x16 = 0x26C - 0x2F7

x8 = 0x234 - 0x2BF

x4 = 0x1E0 - 0x26B

TLP Processing Hints (TPH) Capability TLP Processing Hints (TPH) Capability Structure

x16 = 0x2F8 - 0x2FF

x8 = 0x2C0 - 0x2C7

x4 = 0x26C - 0x273

Address Translation Services (ATS) Capability Address Translation Services Extended Capability (ATS) in Single Root I/O Virtualization and Sharing Specification

x16 = 0x308 - 0x 313

x8 = 0x2D0 - 0x2DB

x4 = 0x27C - 0x287

Access Control Services (ACS) Capability Access Control Services (ACS) Capability

x16 = 0x314 - 0x323

x8 = 0x2DC - 0x2EB

x4 = 0x288 - 0x297

Page Request Services (PRS) Capability Page Request Services (PRS) Capability

x16 = 0x324 - 0x32B

x8 = 0x2EC - 0x2F3

x4 = 0x298 - 0x29F

Latency Tolerance Reporting (LTR) Capability Latency Tolerance Reporting (LTR) Capability

x16 = 0x32C - 0x333

x8 = 0x2F4 - 0x2FB

x4 = 0x2A0 - 0x2A7

Process Address Space (PASID) Capability Process Address Space (PASID) Capability Structure

x16 = 0x46C - 0x477

x8 = 0x434 - 0x43F

x4 = 0x3E0 - 0x3EB

Data Link Feature Extended Capability Data Link Feature Extended Capability

x16 = 0x478 - 0x483

x8 = 0x440 - 0x44B

PTM Capability Structure

Precision Time Management (PTM) Capability

x16 = 0x484 - 0x4EB

x8 = 0x44C - 0x4B3

PTM Requestor Capability Structure (VSEC)


  • x16 core is mapped to port 0 ->x16(Port0)
  • x8 core is mapped to port1 -> x8(Port1)
  • x4 cores are mapped to port2 and port3 -> x4(Port2,3)