F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents Eye Viewer

The F-Tile Debug Toolkit supports the Eye Viewer tool that allows you to measure the eye height margin for each channel. The Eye Viewer tool performs the eye measurement at BER = 1e-12, 95% confidence level.

Note: The F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Eye Viewer feature of the Debug Toolkit does not support independent error sampler for performing eye margining performed on the actual data path. As a result, eye margining may produce uncorrectable errors in the data stream and cause the LTSSM to go to the Recovery state. You may mask out all errors (example AER registers) while performing eye margining and reset all error counters, error registers etc. after margining gets completed.
  1. To run Eye Viewer for a lane, select the lane from the Collection table.
  2. Select the Eye Viewer tab in the channel parameter window of the lane.
  3. Select Eye Height, Eye Width or both options.
  4. Click Start to begin the eye measurement for the selected lane.
  5. The messages window displays information messages to indicate the eye view tool's progress.
  6. Once the eye measurement completes, the eye height results are displayed.
Figure 87. Eye Viewer Results

To reduce the repetitive steps to run eye viewer for more than one lanes, select the lanes from the Collection table, right click and select Start. The eye viewer runs for the selected lanes sequentially.

Figure 88. Eye Viewer Results