F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents Direct User Avalon-MM Interface (Byte Access)

Table 23.  User Avalon-MM Control Register Bit Description
Bit Name Description Access Type Default Value
31:29 RSVD1 Reserved RO 0x0
28:18 k_vf Select the virtual function number RW 0x000
17 k_vf_select To access the virtual function registers, this bit should be set to one. RW 0x0
16:2 RSVD2 Reserved RO 0x0000
1 k_shadow_select

Valid only when d_vsec_select is zero.

If set, it allows the access to shadow registers in PCIe configuration space.

If cleared, it allows the access to standard PCIe configuration registers.

RW 0x0
0 k_vsec_select

If set, it allows the access to Intel VSEC registers

RW 0x0

For Physical Function's configuration space registers access, your application needs to specify the offsets of the targeted Physical Function registers. For example, if the application wants to read the MSI Capability Register of Physical Function 0, it issues a read with address 0x0050 to target the MSI Capability Structure of Physical Function 0.

Figure 43. PF Configuration Space Register Access Timing Diagram
For Virtual Function configuration space register access,your application needs to first specify the VF number of the targeted configuration registers. The application needs to program the User Avalon-MM Port Configuration Register at offset 0x1406A accordingly. For example, to read VF3's MSI-X Capability registers of Physical Function 0, your application needs to:
  1. Issue a user Avalon-MM Write request with address 0x1406A and data 0xE ( vf_num[28:18] = 3, vf _select[17] = 1, vsec[0]=0).
  2. Issue a user Avalon-MM Read request with address 0xB0 to access VF3 registers of Physical Function 0. In the case of Physical Function 1, the address is 0x10B0.
Figure 44. VF Configuration Space Register Access Timing Diagram
Note: You need to reprogram the User Avalon-MM Control Register to access PF registers (after accessing VF registers).

For Intel-defined VSEC access, your application needs to program the VSEC field (0x14068 bit[0]) first. Then all accesses from the user Avalon-MM interface starting at offset 0xD00 is translated to VSEC configuration space registers.

Figure 45. VSEC Register Access Timing Diagram