F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

5.8. 10-bit Tag Support Interface

When the Enable 10-bit tag support interface option is enabled, the IP enables the port p#_10bits_tag_req_en_o [7:0] (one bit per PF) to indicate the 10-bit tag requester enable field is enabled in the configuration space (bit [12] of the Device Control 2 register). For more details, refer to the PCI Express Base Specification Revision 4.0.

Table 70.  Completion Timeout Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p0_10bits_tag_req_en_o[7:0] Output EP coreclkout_hip

One bit per PF. Indicates the 10-bit tag requester enable field in the Device Control 2 register of that PF is enabled.