F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents Additional Debug Tools

Use the Hard IP reconfiguration interface and PHY reconfiguration interface on the F-Tile Avalon® -ST IP for PCI Express to access additional registers (for example, receiver detection, lane reversal etc.).

Figure 80. Register Access for Debug