F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

3.7. Power Management

Software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management output signals indicate the current power state. The IP core supports the two mandatory power states: D0 (full power) and D3 (preparation for a loss of power). It does not support the optional D1 and D2 low power states.

The correspondence between the device power states (D states) and link power states (L states) is as follows:
Table 20.  Device and Link Power States Relationship
Device Power State Link Power State
D0 L0
D1 (not supported) L1
D2 (not supported) L2
D3 L1, L2/L3 Ready

The F-Tile Avalon Streaming Intel FPGA IP for PCI Express IP core supports the required D0 and D3 Power Management states. It does not support the optional D1 and D2 Power Management states. The software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management interface transmits the D-state to the Application Layer.

Endpoint D3 Entry

  1. The power management software must ensure that all outstanding non-posted request have received their associated completions by polling that Transaction Pending bit in the Device Status register. Only then, it can put a function into D3hot state by writing the appropriate value into the PowerState field of its Power Management Control and Status Register.
  2. The link is forced to L1 state when the function changes to D3hot state. In this state, the function can only initiate PME or PME_TO_ACK Messages and can only respond to configuration request or the PME_Turn_Off Message.
  3. The power management software sends the PME_Turn_Off Message to the Endpoint to initiate power down. The delivery of the message TLP causes the link to transition to L0 and the Message is also passed on to the Avalon-ST RX interface.
  4. The IP core auto transmits a PME_TO_Ack Message to acknowledge the Turn Off request.
  5. When ready for power removal D3cold, the application logic in Endpoint asserts p#_app_ready_entr_l23_i. The IP core then sends the PM_Enter_L23 DLLP and initiates the Link transition to L23 Ready.
  6. The reference clock and power can finally be removed when the link has transitioned to the L23 Ready state. The link then enters L3 state if auxiliary power VAUX is not detected or the p#_sys_aux_pwr_det_i signal is de-asserted. If the reference clock and power are not turned off and the p#_sys_aux_pwr_det_i signal is asserted, the link enters L2 state.
Figure 36. Link transition to L2/L3 Ready

Endpoint D3 Exit

  1. Endpoint L1 Exit:
    • Host initiate: Power management software can write to the PowerState field of the function’s Power Management Control and Status (PMCSR) register to change its PM state to D0. Alternatively, the host can initiate link retrain, link disable or hot reset for L1 exit.
    • Device Initiate: For the Endpoint to exit the D3 state, the PME_en bit in the (PMCSR) register needs to be set first. The Application Layer can then request a wake-up event by asserting apps_pm_xmt_pme_i, which causes the IP core to transmit a PM_PME Message. In addition, the IP core sets the PME_status bit in the PMCSR register to notify software that it has requested the wake-up. The PCIe Link states are indicated on the power management interface. The LTSSM state is indicated on the ltssm_stateoutput.
  2. Endpoint L2 Exit: The host system or root port transits into Detect link state and starts to send Electrical Idle order set upon power-up. When the endpoint receives Electrical Idle order set during the L2 link state, it triggers a reset to the PCIe IP core before transit in to Detect link state.
  3. Endpoint L3 Exit: A power cycle to FPGA is required to exit L3 state.
Figure 37. Application Layer requests a wake-up event by asserting apps_pm_xmt_pme_i