F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

7.7.1. PIPE Mode Clock Signal

The PIPE clocks signals as shown below are generated for PCIe IP and each of them correspond to the P0/P1/P2/P3 Core.
  • i_pclk_x4_l12 - P3 Core
  • i_pclk_x4_l4 - P2 Core
  • i_pclk_x8_l8 - P1 Core
  • i_pclk_x16_l0 - P0 Core
Depending on the configuration, only the i_pclk_x* on active cores need to be driven at proper clock frequency according PCIe link speed as shown below. For the i_pclk_x* on inactive cores, keep the clock frequency at 125 MHz (the default value). Please note that these clocks are sourced from VIP. For example, Root Port BFM users need to ensure the clock frequency driving the change properly along with PCIe link speed.
  • Gen1 : 125 MHz
  • Gen2 : 250 MHz
  • Gen3 : 500 MHz
  • Gen4 : 1000 MHz

The following is an example where the PCIe configuration is Gen4 2x8 with i_pclk_x16_l0 and i_pclk_x8_l8 are driven by clocks sourced from Root Port BFM module. In this example, the P0 and P1 cores are active and the source clocks frequency must be driven from 125 MHz (Gen1) and stepping up to 1000 MHz (Gen4). The P2 and P3 cores are inactive, thus i_pclk_x4_l4 and i_pclk_x4_l12 are kept at 125 MHz.

Figure 75. PIPE Clocks Connectivity and Settings in Gen4 2x8 Mode