F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 5/15/2024
Document Table of Contents

7.7.2. PIPE Mode Reset Signal To Verification IP (VIP)

The o_p1__prot_f2t_ssr signals are generated for PCIe IP to perform PIPE reset on VIP. Please refer to the table below to connect the o_p1__prot_f2t_ssr signals to VIP depending on the selected topology mode.

Table 113.  Connecting o_p1__prot_f2t_ssr signals to VIP
Mode VIP Core0 VIP Core1 VIP Core2 VIP Core3
1 x4 o_p1__prot_f2t_ssr[6:3] N/A N/A N/A
1 x8 o_p1__prot_f2t_ssr[10:3] N/A N/A N/A
1 x16 o_p1__prot_f2t_ssr[18:3] N/A N/A N/A
2 x8 o_p1__prot_f2t_ssr[10:3] o_p1__prot_f2t_ssr[18:11] N/A N/A
2 x4 o_p1__prot_f2t_ssr[6:3] o_p1__prot_f2t_ssr[10:7] N/A N/A
4 x4 o_p1__prot_f2t_ssr[6:3] o_p1__prot_f2t_ssr[14:11] o_p1__prot_f2t_ssr[10:7] o_p1__prot_f2t_ssr[18:15]
Figure 76. PIPE Mode Reset Signal to VIP in Gen4 2x8 Mode