AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

Download PDF
ID 683092
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

PCB Design Guidelines

The interconnect between the MIPI TX and RX devices must be designed with caution. The interconnect includes PCB traces, connectors (if any), and cable media (typically flex-foils).

Signal quality guidelines are as follows:

  • Match the electrical length of all pairs as close as possible to maximize data valid margins.
  • Place the passive components as close as possible to the FPGA. Avoid any stub when placing the passive resistors on the high-speed signal trace. Minimize the stub length from the low-power signal trace to high-speed signal trace.
  • Use the on chip termination feature on FPGA I/O whenever possible.
  • The reference characteristics impedance level per line is 100 Ω for differential and 50 Ω for single-ended. Control the impedance of the trace on the PCB to avoid impedance mismatch between the driver output impedance and input impedance of the receiver over the operating frequency.
  • Keep the traces matched in lengths and as short as possible. The flight time for signals across the interconnect should not exceed 2 ns.
  • Ensure equal length for all high-speed differential traces. The differential channel is also used for low-power single-ended signaling. Intel recommends applying only very loosely coupled differential transmission lines.
  • If probe points are required, ensure they are in line with the trace and not creating a transmission line stub.
  • Do not place noisy signals (example: voltage regulator module, clock generator) over or near MIPI signals.
  • Use the I/O standards supported for the FPGA I/O as listed in the I/O standards for MIPI D-PHY Implementation table.
Related Information
Level Two Title