The passive resistor network in this application illustrates and validates the IBIS simulations. You can use the passive resistor network to build a FPGA I/O based compatible MIPI D-PHY for receiving or transmitting both high-speed and low-power signals using various FPGA GPIO connected. The passive resistor network is capable to enable an electrically compatible connection between Intel FPGA I/O to a MIPI D-PHY TX or RX device via MIPI D-PHY interface.
|FPGA Implementation||Passive Resistor Value (Ω)|
|FPGA unidirectional receiver implementation||300||100||—||—||—|
|FPGA unidirectional transmitter implementation||—||—||150||60||100|
|Device||Supported Data Rate (Mbps)|
|Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP||840|
|Intel® MAX® 10||720|
Intel recommends performing HSPICE/IBIS simulations to verify the signal quality based on your specific system setup and PCB info at the desired operating frequency.
Actual achievable frequency depends on design- and system-specific factors. Perform HSPICE/IBIS simulation based on your specific design, system setup, and PCB info to determine the maximum achievable frequency.
The MIPI D-PHY passive solution with different approaches (I/O, passive network, and FPGA devices) are validated using multiple demo boards. You can use the following demo boards as reference:
- Intel 10M50 Evaluation Kit, EK-10M50F484 (available March 2016 onwards)
- Arrow DECA Intel® MAX® 10 Evaluation Kit
For more information about the demo boards, contact your local Intel sales representatives.
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