Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices
Figure 15. Cyclone® IV and Intel® Cyclone® 10 LP HS-TX Mode Eye Diagram Measured At MIPI D-PHY Receiver Die At 840 MbpsTrue (P) and Inverted (N) signals are plotted in purple and blue. Differential signal (P-N) is plotted in green.
Figure 16. Cyclone® IV and Intel® Cyclone® 10 LP LP-TX Mode Waveform Measured At MIPI D-PHY Receiver Die for LP11 and LP00 States at 10 MbpsDP signal is shown in pink and DN signal is shown in yellow. The DN signal (yellow) overlaps with the DP signal (pink) because both signals are driven on the same state (LP11, LP00).
Figure 17. Cyclone® IV and Intel® Cyclone® 10 LP LP-TX Mode Waveform Measured At MIPI D-PHY Receiver Die for LP10 and LP01 States at 10 MbpsBoth DP and DN signals are not overlapped because they are driven out of phase (LP10, LP01).
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