IBIS simulation using HyperLynx is performed to show the link simulation between the MIPI D-PHY, transmission line, passive resistor network, and FPGA I/O for Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® Intel® MAX® 10 devices. The simulation demonstrates the following signaling modes with the passive resistor networks setups:
- Input and output differential and common-mode voltage levels for high-speed signaling
- Single-ended input and output high and low voltage levels for low-power signaling
During normal operation, either high-speed or low-power signaling can drive a lane. The states for high-speed lane are Differential-0 and Differential-1. The two single-ended lines in low-power lane states can drive a different or same state depending on the mode of operation. The low-power lane can drive four possible states: LP00, LP11, LP01 and LP10.
The high-speed mode is simulated at 840 Mbps for Cyclone® IV, Cyclone® V, and Intel® Cyclone® 10 LP devices, and 720 Mbps for Intel® MAX® 10 device. The low-power mode is simulated at 10 Mbps for Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices. The simulation uses simple transmission line that assumed to have the characteristics impedance of 50 Ω with 500 ps transmission delay.
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