AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

FPGA As Transmitter: Simulation Results

The simulated waveforms for the Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices are based on the recommended setup.

The I/O standards used in the FPGA I/O pins are compliant to the following voltage levels as defined for high-speed or low-power MIPI D-PHY RX device under typical conditions:

  • High-speed signals—Input differential (VID) and common mode (VICM) voltage levels
  • Low-power single-ended signals—Input voltage high (VIH) and input voltage low (VIL) signals

The signal quality for high-speed signal is better with less jitter compared to the high-speed signal when FPGA acts as the receiving interface. The 100 Ω differential termination resistor at the load provides good impedance matching to the characteristic impedance of the transmission line.


Section Content
FPGA As Transmitter: Simulation Results Using Cyclone IV and Intel Cyclone 10 LP Devices
FPGA As Transmitter: Simulation Results Using Cyclone V Devices
FPGA As Transmitter: Simulation Results Using Intel MAX 10 Devices

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