AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

ID 683092
Date 4/03/2019
Document Table of Contents

FPGA As Transmitter: Simulation Results

The simulated waveforms for the Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices are based on the recommended setup.

The I/O standards used in the FPGA I/O pins are compliant to the following voltage levels as defined for high-speed or low-power MIPI D-PHY RX device under typical conditions:

  • High-speed signals—Input differential (VID) and common mode (VICM) voltage levels
  • Low-power single-ended signals—Input voltage high (VIH) and input voltage low (VIL) signals

The signal quality for high-speed signal is better with less jitter compared to the high-speed signal when FPGA acts as the receiving interface. The 100 Ω differential termination resistor at the load provides good impedance matching to the characteristic impedance of the transmission line.