AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

ID 683092
Date 4/03/2019
Document Table of Contents

Overview on MIPI Operation

The D-PHY provides a synchronous connection between a master and slave. The minimum PHY configuration consists of a clock and one or more data signals. The D-PHY uses two wires per data lane and two wires for the clock lane. The lane can operate in a high-speed (HS) signaling mode for fast-data traffic and low-power (LP) signaling mode for control purpose.

The maximum data rate that can be supported in high-speed signaling is determined by the performance of the transmitter, receiver, and interconnect implementations. In practice, the typical implementation has a bit rate of approximately 500-800 Mbps per lane in high-speed mode for passive D-PHY. However, for some D-PHY applications, the bit rate can go up to 1.5 Gbps per lane. The maximum data rate in low-power mode is 10 Mbps.

The three possible implementations for connecting MIPI / D-PHY compliant device to Intel FPGAs are as follows:

  • Use of an external D-PHY ASSP (for example Meticom MC2000x and MC2090x devices) as an active level shifter
  • Use passive resistor network to create the compatible D-PHY with FPGA general-purpose I/O (GPIO)
  • Use FPGA transceiver I/O to achieve higher data rate

This application note discusses the implementation using passive resistor network to achieve the lowest cost implementation.

The D-PHY can support bidirectional data transmission or unidirectional data transmission. CSI-2 protocol only requires unidirectional data transmission. Thus this implementation of a MIPI D-PHY compatible solution for Intel’s low cost FPGAs only supports unidirectional data transmission.

  • Receiving interface—FPGA I/O receives the high-speed or low-power signaling from a MIPI D-PHY transmitter (TX) device such as camera sensor or imager
  • Transmitting interface—FPGA I/O transmits the high-speed or low-power signaling to a MIPI D-PHY receiver (RX) device such as a host or display

The high-speed differential signaling and low-power single-ended serial signals have different electrical characteristics. This application note covers the recommendation of the I/O standard for the FPGA I/O to emulate a MIPI D-PHY RX or TX, and provide an electrically compatibility between FPGA I/O and the MIPI interface. The single-ended mode uses LVCMOS or HSTL I/O standard for low-power mode, and differential I/O standard (LVDS) for high-speed mode. Resistors are used to connect, isolate, terminate, and level set to construct the compatible D-PHY.

Did you find the information on this page useful?

Characters remaining:

Feedback Message