Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
Figure 10. HS-RX Mode Eye Diagram Measured At Intel® MAX® 10 FPGA Receiver Die At 720 MbpsTrue (P) and Inverted (N) signals are plotted in yellow and pink. The P and N signals are overlapped. Differential signal (P-N) is plotted in blue.
Figure 11. LP-RX Mode Waveform Measured At Intel® MAX® 10 FPGA Receiver Die for LP11 and LP00 States at 10 MbpsDP signal is shown in blue and DN signal is shown in red. The DN signal (red) overlaps with the DP signal (blue) because both signals are driven on the same state (LP11, LP00).
Figure 12. LP-RX Mode Waveform Measured At Intel® MAX® 10 FPGA Receiver Die for LP10 and LP01 States at 10 MbpsBoth DP and DN signals are not overlapped because they are driven out of phase (LP10, LP01).
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