AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

ID 683092
Date 4/03/2019
Document Table of Contents

FPGA As Receiver: Simulation Results

The simulated waveforms for the Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices are based on the recommended setup. The I/O standards used in the FPGA I/O pins are compliant to the following voltage levels transmitted from the MIPI D-PHY TX device under typical conditions:

  • High-speed signals—Output differential (VOD) and common mode (VOCM) voltage levels
  • Low-power single-ended signals—Output voltage high (VOH) and output voltage low(VOL) signals