AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

FPGA As Receiver: HS-RX and LP-RX Modes Simulation

In the HS-RX and LP-RX mode simulation, the FPGA acts as a receiver to receive the MIPI D-PHY high-speed and low-power signals from MIPI D-PHY TX device in a single lane. The differential termination is fixed at 300 Ω across the LVDS pair in a single lane. The termination is set high to avoid the complexity of switching in and out of the high-speed mode termination. The termination supports the required signal quality at the targeted data rates although the termination does not match the characteristics impedance of the transmission line. The 300 Ω load between the lines minimizes loading in the low-power mode and in the LP01 or LP10 state. The two fixed series termination resistors are used for the low-power signals.

Figure 3. FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit
Level Two Title