AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

ID 683092
Date 4/03/2019
Document Table of Contents

FPGA As Receiver: HS-RX and LP-RX Modes Simulation

In the HS-RX and LP-RX mode simulation, the FPGA acts as a receiver to receive the MIPI D-PHY high-speed and low-power signals from MIPI D-PHY TX device in a single lane. The differential termination is fixed at 300 Ω across the LVDS pair in a single lane. The termination is set high to avoid the complexity of switching in and out of the high-speed mode termination. The termination supports the required signal quality at the targeted data rates although the termination does not match the characteristics impedance of the transmission line. The 300 Ω load between the lines minimizes loading in the low-power mode and in the LP01 or LP10 state. The two fixed series termination resistors are used for the low-power signals.

Figure 3. FPGA As Receiver HS-RX and LP-RX Modes IBIS Simulation Circuit