AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

ID 683092
Date 4/03/2019
Public
Document Table of Contents

FPGA As Transmitter: HS-TX and LP-TX Modes Simulation

In the HS-TX and LP-TX mode simulation, the FPGA acts as a MIPI D-PHY TX device. The MIPI D-PHY RX device is represented by the package parasitic components with a worst case capacitive load of 3.0 pF.

When the interface is in high-speed mode, the MIPI D-PHY RX device presents a 100 Ω differential termination in this simulation (as shown in the FPGA As Transmitter HS-TX Mode IBIS Simulation Circuit diagram). When the common-mode of the lines indicates that the interface is in low-power mode, the 100 Ω termination is switched to high Z, which is not shown in the LP-TX mode IBIS simulation circuit (as shown in the FPGA As Transmitter LP-TX Mode IBIS Simulation Circuit diagram). In this simulation, the MIPI D-PHY high-speed receiver is turned off during the low-power mode operation, thus the input differential termination is removed.

The IBIS simulation uses the buffers in different modes as follows:

  • High-speed mode
    • A differential buffer is used to transmit signals.
    • Two single-ended buffers are configured as input mode to act as tri-stated outputs.
  • Low-power mode
    • A differential buffer is configured as input mode to act as tri-stated output.
    • Two single-ended buffers are used to transmit signals.
Figure 13. FPGA As Transmitter HS-TX Mode IBIS Simulation Circuit
Figure 14. FPGA As Transmitter LP-TX Mode IBIS Simulation Circuit

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