AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator

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ID 683083
Date 7/16/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
1. Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator x
1.1. List of Abbreviations 1.2. Introduction 1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE) 1.4. Intel® Stratix® 10 FPGA Package Physical Design 1.5. Physical Package Structure 1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters 1.7. Intel® Stratix® 10 Compact Thermal Model (CTM) 1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD) 1.9. Intel® Stratix® 10 Thermal Design Process 1.10. Early Power Estimator (EPE) 1.11. Transceiver Channel Spreading 1.12. Thermal Parameter Dependencies 1.13. Intel® Stratix® 10 Thermal Design Example 1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
1.13. Intel® Stratix® 10 Thermal Design Example x
1.13.1. CFD Analysis Setup 1.13.2. CFD Analysis Results 1.13.3. Transceiver Channel Placement Optimization 1.13.4. TSD offset Assessment for the Example
1. Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator

1.11. Transceiver Channel Spreading

Reducing the thermal resistances of the package in each design improves the efficiency of the cooling system. One way to achieve this is by spreading out the transceiver channels or use an extra transceiver tile to reduce the power density of a transceiver die. Targeted spreading can reduce ΨJC and increase ΨCA, thereby reducing the cooling requirement.

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