AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator

ID 683083
Date 7/16/2021

1.2. Introduction

An Intel® Stratix® 10 device has a Multi-Chip Module (MCM) structure. It can contain between two and nine dies. One die is always the main FPGA core fabric die, and there can be between one and six transceiver dies, and up to two High Bandwidth Memory (HBM) dies. Due to complex construction and no uniform power density in some of the dies, the thermal engineering of an Intel® Stratix® 10 device requires a specific process and familiarity with the following:

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