AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator

ID 683083
Date 7/16/2021

1.9. Intel® Stratix® 10 Thermal Design Process

The Stratix 10 FPGA thermal design process consists of the steps shown below:
Figure 5.  Intel® Stratix® 10 Thermal Design Process
  • Supply Design Information to EPE

    This is the first step in the thermal design process of an Intel® Stratix® 10 device that provides the tool with the necessary data to estimate the power dissipation of each die. The inputs include the FPGA design information as well as the thermal design requirements of TA and TJ-MAX and power margin selection.

  • Obtain Thermal Design Parameters

    The EPE tool provides the thermal design parameters. The power dissipation of the transceiver die is provided as a constant value, but the main core die power dissipation is provided as a function of its junction temperature and it should be used accordingly in the CFD analysis.

  • Obtain CTM

    Obtain the applicable CTM for the CFD analysis. Each CTM is provided with the maximum number of dies possible in a package. Unused dies can be ignored and left in the model without affecting the end results.

  • Run CFD Analysis

    Model the system in the CFD tool and apply all the applicable power values to the corresponding dies. The CFD solution provides the core die TDP and temperature and the TCASE. The transceiver and HBM die temperatures cannot be predicted by the CFD and are calculated manually.

  • Calculate Junction Temperatures and Ψ CA

    Junction temperatures of all the dies and ΨCA of the cooling solution are calculated using the following equations:

    You can verify the CFD modeling results by comparing the above calculated ΨCA with the value provided by the EPE tool for the corresponding TTDP. If the two values are the same, then the calculated TJ = TJ-MAX.